Keynotes

Title: The Reconfigurable Future of Accelerators (or Wishful Thinking?)

Date & Time: 03 Sep 2025, 08:50-09:50 CET

Abstract:
Reconfigurable accelerators have long held the promise of near-ASIC efficiency while retaining the programmability missing from fixed-function accelerators. Over the past decade, significant architectural and compiler breakthroughs, including key contributions from our research group on CGRA-class designs such as the HyCUBE and PACE architectures, and the Morpher compiler framework, have significantly improved throughput, energy efficiency, and programmability. Despite these advances, the accelerator landscape remains largely dominated by specialized domain-specific accelerators. Key barriers to wider adoption persist, notably fragmented software ecosystems lacking a universal instruction-set architecture and programming model, complex compilers, and the high area and power costs associated with reconfiguration. However, emerging trends in rapidly evolving AI algorithms, characterized by irregular sparsity and frequent model updates, highlight the unique advantage of reconfigurable fabrics. A paradigm shift from current static mapping approaches to dynamic, data-driven scheduling methods that fully leverage runtime reconfigurability could offer a distinct edge over GPUs and specialized AI accelerators. In this talk, I will outline the current state of the technology, examine the critical adoption barriers, and present a strategic roadmap that could make reconfigurable accelerators the default fabric of the 2030s.

Biography:
Tulika Mitra is Provost's Chair Professor of Computer Science and Vice-Provost (Academic Affairs) at the National University of Singapore (NUS). Her research focuses on the design automation of smart, energy-efficient, safety-critical embedded computing systems. Her work is characterized by a systems-centric approach spanning hardware and software to advance accelerator design, power/thermal management in heterogeneous computing systems, and WCET analysis of real-time systems. She has served as the Editor-in-Chief of ACM Transactions on Embedded Computing Systems, General/Program Chair of ICCAD, and General Chair of ESWEEK. Tulika has been recognized with the Embedded Systems Week (ESWEEK) Test-of-Time Award, several best paper award or candidates in top conferences, Indian Institute of Science S. K. Chatterjee Award for Outstanding Woman Researcher, and ACM SIGDA Distinguished Service Award among others.

Title: Ubiquitous AI by the Agile Generation of Inference Solutions

Date & Time: 04 Sep 2025, 13:30-14:30 CET

Abstract:
AI is rapidly becoming a prominent aspect of our lifes and being adopted across a broad spectrum of applications. This includes a rising interest in classic embedded application domains, such as communications, sensor intelligence and robotics. The problems at hand are very concrete. The operational requirements faced for deployment come in the form of hard constraints, are extremely diverse and demand customization to reap in the specialization dividend. FPGA devices offer an ideal platform for tightly integrating application-specific AI inference solutions within a custom system context that can fuse it with sensor and actuator control as well as classic signal processing and control blocks. Creating momentum for the development of these systems calls for an agile tool stack for exploring, evaluating and deploying these custom AI solutions. FINN, in conjunction with the powerful quantization tool Brevitas, has come a long way and is maturing into providing such a tool stack. This keynote recollects the journey of growing FINN beyond its original confines of binarized convolutional neural networks. On the way, numerous lessons have been learned including the attractive mapping of higher-precision compute, algorithmic optimization opportunities, and the need for an easy custom extension interface for injecting custom transformations and hardware operators. Overall, the range of intrinsically supported topologies and operators has grown consistently. The attained level of agility is illustrated by highlights in the enablement of generating topologies with transformer characteristics.

Biography:
Thomas is a principal engineer and the FINN project lead at AMD Research. Thomas earned a PhD from TU Dresden in 2011. He worked as a postdoctoral researcher both there and at the Systems Group of ETH Zürich. He also enjoyed an EU-funded Individual Maria-Skłodowska-Curie Fellowship at the Xilinx Research Labs in Dublin. His scientific background is computer arithmetic, application acceleration and systems design using FPGAs. His current focus lies on advancing FINN, a tool for the generation of custom embedded neural-network inference solutions.

Title: Adaptable Integrated Circuits for an evolving world

Date & Time: 03 Sep 2025, 13:30-14:30 CET

Abstract:
We have entered a new era where computing is not only everywhere, but requires energy efficiency and fast adaptability. Hardware - software co-design is not an option anymore and is already not sufficient enough. Maximizing efficiency while adapting to new usage, specifications and threats is pushing for adaptive hardware right within mass production ICs. Structural megatrends imply an exponential requirement for adaptive SoCs and ASICs: growing demand of long lifetime ICs for defense, newspace, industrial and mobility; end of Moore's law and increasing difficulties to find talents. There is a need for adaptation during IC lifetime, adaptive accelerators / custom compute, lowering design cycles, pushing design decisions to after tapeout and waste reduction. Embedded FPGA (eFPGA) are answering those challenges by providing programmable logic right inside SoCs and ASICs. In this talk, I will tell the story of eFPGAs, explain the current state of the technology, go through major differentiators and talk through usage examples amongst security, automotive, industrial, space and glimpse into the close future with heterogenous chiplets design.

Biography:
Since 2016, Yoan Dupret is the Managing Director and CTO of Menta, the leader in embedded FPGA IP cores for integrated circuits and smart sensors. Spanning a 20+ years career in the semiconductor industry, prior to his position at Menta, Yoan held various managerial and technical positions at DelfMEMS, Samsung, CSR, Infineon and Altis Semiconductor. He has worked on a variety of topics including yield modeling, transistor compact models, EDA, RF MEMs and filed-programmable logic. He holds a PhD from CentraleSupelec (France), an Engineering degree (MSEE) from ESEO (France) and a MD from University Paris 6 (France).

Title: An Ode to Cost: The Quiet Force Behind FPGA Evolution

Date & Time: 04 Sep 2025, 08:30-09:30 CET

Abstract:
Over the past three decades, FPGA architecture has undergone remarkable transformation—from basic glue logic to enabling some of the most demanding workloads in networking, wireless, and embedded compute. While performance and power are often cited as primary design goals, this talk will argue that cost—in its many forms—has been the true, consistent force shaping FPGA evolution. From architectural choices and process technology to software tooling and market segmentation, cost optimization has quietly but fundamentally driven innovation across generations.
We will explore how key components of FPGAs have advanced under cost pressures, and how this principle guided hardware and software innovations in the Agilex family—yielding the largest single-generation performance-per-watt improvements in Altera's history. Finally, we'll look ahead to the next decade, examining how a cost-centric mindset can uncover new opportunities and steer the future of reconfigurable computing.

Biography:
Ilya Ganusov is a Fellow and Chief Silicon Architect at Altera. He joined Intel's FPGA division in 2018 to lead the development of the Agilex FPGA core architecture and drive application-specific innovations for AI, high-performance computing, and wireless communications. Following Intel's spin-off of Altera as an independent company in 2024, Ilya took on responsibility for defining overall FPGA architecture strategy and advancing research in architectural tools and methodologies. Before joining Intel and Altera, Ilya held senior technical roles at Xilinx, where he led initiatives to improve performance and power efficiency across multiple FPGA generations, and at Achronix, where he contributed to the design of asynchronous FPGAs. Ilya holds over 40 granted patents and has authored numerous publications spanning FPGA architectures, CAD algorithms, memory systems, and circuit design. He earned his M.S. and Ph.D. in Electrical and Computer Engineering from Cornell University, and a B.S. in Electrical Engineering from Ivanovo State Power Engineering University in Russia. His contributions have been recognized with the 2021 Intel Achievement Award and the 2017 Xilinx Ross Freeman Award for technical innovation in FPGA architecture.