Program Overview

Detailed Program

Monday Sep 1

• 12:30 – 17:30 Registration
  
• 13:30 – 15:00 Workshops and Tutorials
  
• 15:00 – 15:30 Coffee Break
  
• 15:30 – 17:30 Workshops and Tutorials
  

Tuesday Sep 2

• 08:00 – 17:30 Registration
  
• 08:30 – 10:30 Workshops and Tutorials
  
• 10:30 – 11:00 Coffee Break
  
• 11:00 – 12:30 Workshops and Tutorials
  
• 12:30 – 13:30 Lunch
  
• 13:30 – 15:00 Workshops and Tutorials
  
• 15:00 – 15:30 Coffee Break
  
• 15:30 – 17:30 Workshops and Tutorials
  
• 17:30 – 19:00 Welcome Reception
  

Wednesday Sep 3

• 08:00 – 18:00 Registration
  
• 08:30 – 08:50 Opening
  
• 08:50 – 09:50 Keynote 1: Tulika Mitra (National University of Singapore)
  
• 09:50 – 10:30 Session 1: Dynamic Reconfiguration
• Virtualization and Dynamic Reconfiguration of Custom Instruction Accelerators (CIA) in RISC-V Embedded Systems
  Bea Healy, Brandon Freiberger, Jonas Kuenstler, King Lok Chung, Emil Cozac, Meinhard Kissich, Gennadiy Knis, Ron Sass, Dirk Koch, Jan Gray and Guy Lemieux
• ReconFormer: A Multi-Level Run-Time Reconfigurable System-on-Chip for Accelerating Transformers
  Je Yang, Gabriele Tombesi, Joseph Zuckerman and Luca Carloni
• 10:30 – 11:00 Coffee Break + Collaborative Projects
  
• 11:00 – 12:30 Session 2: Architectures 1: Logic Optimizations in FPGA Architectures
• FLAIC: A Novel FPGA Logic Architecture via Fine-Grained Cut Topology Analysis
  Xianfeng Cao, Huizhen Kuang, Yuanqi Wang and Lingli Wang
• Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
  Xilai Dai, Junius Pun, Grace Zgheib, Mahesh Iyer, Andrew Boutros, Vaughn Betz and Mohamed Abdelfattah
• DEFA: Design Space Exploration for FPGA Overlay Accelerators through Frequency Prediction and Bayesian Optimization
  Qilong Zhu, Yunfei Dai, Shiyan Bi, Huizhen Kuang, Dylan Wang, Wenbo Yin and Lingli Wang
• FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs
  Shashwat Khandelwal, Jakoba Petri-König, Thomas B Preußer, Michaela Blott and Shanker Shreejith
• Multiplexer Optimizations for Virtex FPGAs Short Paper
  Nicolai Fiege, Martin Hardieck and Peter Zipf
• 12:30 – 13:30 Lunch + Collaborative Projects
  
• 13:30 – 14:30 Keynote 2: Yoan Dupret (Menta)
  
• 14:30 – 15:00 Session 3: Architectures 2: Special Structures
• Identifying SAT Resilient Blocks through LUT Switching Analysis for Breaking Compound Logic Locking Schemes
  Binbin Wang, Xinmu Wang, Xinyu Zhang, Shibo Tang, Huisi Zhou and Wei Hu
• URAM-based Asynchronous FIFO Design for Improved Throughput and FPGA RAM Usage Short Paper
  Martim Rosado, Pedro Tomás, Nuno Roma and André David
• 15:00 – 16:30 Industry Event Session
  
• 16:30 – 18:00 PhD Forum + Demo Night and Reception
• Energy-Efficient DNNs on FPGAs for Edge-Cloud Computer Vision PhD Forum
  Qaisar Farooq and Idilio Drago
• Towards Accelerated Healthcare Federated System Through Heterogeneous Accelerators PhD Forum
  Giuseppe Sorrentino and Davide Conficconi
• Using Data to Reduce Uncertainty in FPGA Routing PhD Forum
  Andrew David Gunter and Steve Wilton
• Maximizing Resource Utilization for Stencil Computing PhD Forum
  Pedro Henrique Di Francia Rosso and Guido Araujo
• Reducing FPGA Placement Runtime by Clustering of Netlist Blocks PhD Forum
  Markus Rein and Dirk Stroobandt
• Interconnection-Aware Resynthesis for Improving FPGA Physical Design PhD Forum
  Xiaoke Wang and Dirk Stroobandt
• Multi-FPGA Programming Using OpenMP Demo Night
  Pedro Henrique Di Francia Rosso and Guido Araujo
• Performance Impact on Reducing Energy Consumption Applying Adaptive Stream-based Entropy Coding on FPGA Demo Night
  Taku Nishikawa, Koichi Marumo and Shinichi Yamagiwa
• Analytical Buffer Sizing for Neural Network Inference Applications on FPGAs Demo Night
  Lukas Stasytis, Felix Jentzsch and Zsolt Istvan
• FPGAs with FABulous - Framework and Chips Demo Night
  Dirk Koch, Myrtle Shah, King Lok Chung, Jonas Kuenstler, Marcel Jung, Jakob Ternes, Asma Mohsin and Gennadiy Knis
• NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA Prototyping Demo Night
  Kyuseung Han, Hyeonguk Jang, Sukho Lee, Sung-Eun Kim, Kyudong Hwang and Jae-Jin Lee
• Continuous Processing of Event-Data with Graph Convolutional Neural Networks Implemented for SoC FPGA Demo Night
  Piotr Wzorek, Kamil Jeziorek, Marcin Kowalczyk, Krzysztof Blachut, Tomasz Kryjak and Marek Gorgon
• Versatile Place and Route with Continuous Routing Runtime Prediction and Smart Route Termination Demo Night
  Andrew David Gunter and Steve Wilton
• Connection Tracking at 400 Gbps Demo Night
  David Vodák, Oliver Gurka, Jiří Matoušek and Daniel Kondys
• Compile in Seconds and Run on FPGA with DynaRapid Demo Night
  Andrea Guerrieri, John Isaac Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic and Paolo Ienne

Thursday Sep 4

• 08:00 – 18:00 Registration
  
• 08:30 – 09:30 Keynote 3: Ilya Ganusov (Altera)
  
• 09:30 – 10:30 Session 4: AI-Based CAD Tools
• From Errors to Solutions: LLM-Powered Command Scripting for FPGA CAD Tools
  Mohamed A. Elgammal and Vaughn Betz
• TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer
  Qin Luo, Xinshi Zang, Evangeline F.Y. Young and Martin D.F. Wong
• GEF: A GNN-Based Evaluation Framework for FPGA Routing Architecture
  Yuanqi Wang, Yunfei Dai, Jiangnan Li, Kaixiang Zhu, Huizhen Kuang, Hao Zhou, Eric Ren, Xifan Tang, Weijun Qin, Tao Li and Lingli Wang
• 10:30 – 11:00 Coffee Break + Poster Session A
  
• 11:00 – 12:30 Session 5: Accelerators
• FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption
  Zhihan Xu, Rajgopal Kannan and Viktor Prasanna
• F2Opt: Novel Fine-Tuning and Folding Algorithms for FPGA-Based DNN Accelerators
  Muhammad Shakeel Akram, Bogaraju Sharatchandra Varma, Vincent Meyers, Mehdi Tahoori and Dewar Finlay
• FPGA-Based MPSoCs for High-Performance Sensor Fusion: Accelerating Covariance Intersection
  Hazem Sharf and Mohamed Hassan
• AffiNiTy: A Multi-Scalar Multiplication Accelerator with a Novel Batched Inversion Architecture
  Tong Wu, Niall Emmart and Oliver Diessel
• EVil: An Efficient Vision-LSTM Accelerator Based on FPGA Short Paper
  Zexuan Deng, Han Jiao, Wenjin Huang and Yihua Huang
• 12:30 – 13:30 Lunch + Poster Session A
  
• 13:30 – 14:30 Keynote 4: Thomas Preusser (AMD)
  
• 14:30 – 15:00 Session 6: Design for Power
• ATAPP: Architecture and Technology Aware Power Predictor for Unseen FPGAs
  Zhigang Wei, Aman Arora, Emily Shriver and Lizy John
• SparseDPD: A Sparse Neural Network-Based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization Short Paper
  Manno Versluis, Yizhuo Wu and Chang Gao
• 15:00 – 15:30 Coffee Break
  
• 15:30 – 16:50 Session 7: Routing
• Programmable Congestion Generator for Evaluating FPGA Interconnect Robustness
  Atreyee Saha, Sandesh Goyal and Aashish Tripathi
• Routino: Accelerating FPGA Routing through Efficient Memory Representation
  Davide Nicolini, Corrado De Sio, Eleonora Vacca and Luca Sterpone
• Open-Source FPGA Routing Runtime Prediction for Improved Productivity via Smart Route Termination
  Andrew David Gunter and Steven Wilton
• Routing Struggle: A Metric to Quantify Routability
  Sadegh Yazdanshenas and Jeffrey Chromczak
• 16:50 – 18:00 Session 8: Applications 1: Soft-Cores & Optimisation
• ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors
  Haoran Wu, Ce Guo, Wayne Luk and Robert Mullins
• Improving Boolean Satisfiability-Based Modulo Scheduling
  Nicolai Fiege and Peter Zipf
• Maximum FPGA - A 32K 32-way Parallel FFT
  Martin Langhammer and Bogdan Pasca
• Cocotb-Pynq: Co-simulating Python+RTL Applications Targeting Pynq Platforms with Cocotb Short Paper
  Gavin Lusby and Nachiket Kapre
• 19:00 – 23:00 Gala Dinner
  

Friday Sep 5

• 08:00 – 15:00 Registration
  
• 08:30 – 09:30 Keynote 5: Maire O'Neill (Queen's University Belfast)
  
• 09:30 – 10:30 Session 9: Applications 2: Vision Applications
• EQViTA: An End-to-End Quantized Vision Transformer Accelerator Implemented on Resource-Constrained FPGAs
  Jiacheng Cao, Jiaqi Guo, Wei Xiong, Jian Wang and Jinmei Lai
• FPGA Stereo Visual SLAM with Efficient Stereo Feature Matching and Key-frame Generation
  Miyuru Thathsara, Damith Anhettigama and Siew Kei Lam
• A High-performance and Resource-Efficient FPGA-based Multi-Object Tracking System Using Event Cameras
  Wei Xiong, Jianfan Zhang, Xingzhe Zhu, Jiacheng Cao, Jian Wang and Jinmei Lai
• 10:30 – 11:00 Coffee Break + Poster Session B
  
• 11:00 – 12:30 Session 10: Architectures 3: Datapath and Soft-Core Enhancements
• Four-Input Lookup Table (LUT4) and Architectural Enhancements Enable Power Efficient Mid-range FPGAs
  Satwant Singh, Michael Schneider, Ziad Aboud, Jonathan Peterson, Senani Gunaratna, Ting Yew, Cindy Lee and Rick Crotty
• Refining Datapath for Microscaling ViTs
  Can Xiao, Jianyi Cheng and Aaron Zhao
• Towards Instruction-Controlled In-Pipeline GEMM Acceleration in a Dual-Issue RISC-V Core for Edge Applications
  Ahmad Othman, Darmen Ilyas, Ahmed Kamaleldin and Diana Goehringer
• Design Space Exploration of Fast RISC-V Processors for Scalable Kilo-Core FPGA Systems
  Riadh Ben Abdelhamid, Vladislav Valek, Kevin Klein and Dirk Koch
• DMA Calypte: Open-Source Ultra-Low Latency DMA Engine for FPGAs Short Paper
  Vladislav Válek, Martin Špinler, Jakub Cabal and Tomáš Martínek
• 12:30 – 13:30 Lunch + Poster Session B
  
• 13:30 – 15:10 Session 11: Neural Networks and Artificial Intelligence
• Hybrid Weightless Neural Networks for Efficient Edge Inference
  Mugdha Jadhao, Alan T. L. Bacellar, Shashank Nag, Igor D. S. Miranda, Felipe M. G. França and Lizy K. John
• Accelerating Transposed Convolutions on FPGA-Based Edge Devices
  Jude Haris and José Cano
• AMD AI Engine Implementations of FAM and SSCA Estimators
  Jingyi Li, Ruilin Wu and Philip Leong
• GAMA: High-Performance GEMM Acceleration on AMD Versal ML-Optimized AI Engines
  Kaustubh Manohar Mhare, Endri Taka and Aman Arora
• NeuGEMM: A Reordering-Free Unified GEMM-Conv2D Accelerator for Lightweight Neuromorphic Processors Short Paper
  Hyeonguk Jang, Sukho Lee, Jae-Jin Lee and Kyuseung Han
• Accelerating K-Means: A Vectorized Approach for AI Engines & Neural Processing Units Short Paper
  Eleonora Cabai, Giuseppe Sorrentino, Marco Domenico Santambrogio and Davide Conficconi
• 15:10 – 15:30 Closing