Exploring the new AMD AUP-ZU3 Academic Platform

Type: Tutorial

Organizers/Speakers: Mario Ruiz, AMD University Program, AMD

This tutorial will introduce the AUP-ZU3, the latest AMD University Program SoC academic platform. This platform is designed to serve education and research, catering for both learners and experienced users. This board can be used in multiple areas, including digital design, computer architecture and embedded systems, among others. The AUP-ZU3 board is powered by a ZU3 AMD Zynq™ Ultrascale+™ MPSoC device and it features a variety of interfaces (I/O) - LEDs, switches, buttons, Pmod™, MIPI, Display Port, etc. - that makes it applicable broadly in academia. It is also supported by the popular open source PYNQ framework. As part of the tutorial, we will cover the Vivado™ design flow and how to target the AUP-ZU3 platform. We will discuss what is new in Vivado and Vitis™ HLS. This will give the audience an idea of the development flow not only for the AUP-ZU3 but also for other adaptive computing devices. Then, we will describe how PYNQ™ - Python productivity for adaptive computing platforms - uses Python and Jupyter™ notebooks to make AMD SoC more accessible. We will demonstrate this with a few examples on the AUP-ZU3 board. We will talk about the latest PYNQ (release 3.1) features and how they help its users be more productive. In the second part, the participants will engage in a hands-on session with the newest AUP-ZU3 board, booting it up and exploring example designs using PYNQ. Advanced users will have the opportunity to design their own overlays and download it onto the board. By participating in this tutorial, attendees will gain valuable practical skills that can be directly applied in educational and research settings.

Workshop on Security for Custom Computing Machines (SCCM)

Type: Workshop

Organizers:
Mirjana Stojilović, Scientist, EPFL, Switzerland
Jeff Goeders, Associate Professor, Brigham Young University, United States

Featured Speakers:

• Durga Lakshmi-Ramachandran, Innovation Director, Keysight Device Security Solutions
  We are moving to an era where quantum computing threatens the confidentiality of current cryptographic protocols, specifically around “harvest now, decrypt later” attacks. Algorithms such as CRYSTALS-Kyber and CRYSTALS-Dilithium, selected as NIST standards, are built on well-studied and mathematically robust foundations. However, strong algorithmic design alone is not enough. A cryptographic system remains vulnerable if the implementation is insecure—algorithmic security does not guarantee implementation security. We will see example on how Fault Injection could be still relevant for PQC.
• Guy Gogniat, Professor, Université Bretagne Sud
  In this talk we will discuss some contributions to the security of processor-based systems in the context of embedded devices. We will discuss a solution to ensure constant-time computation and how the cache architecture can be extended to ensure constant-time properties. This approach exploits the software-hardware interface by extending ISA RISC-V to lock and unlock some sensitive data in the cache.
• Jonathan Graf, CEO, Graf Research
  Dr. Jonathan Graf, CEO of Graf Research, will share how Graf Research is developing a new generation of configurable computing tools for electronic design automation and verification—tools that create independent, trustworthy views of FPGA configuration and silicon correctness. Among these innovations is a method for bitstream equivalence checking, Enverite PV-Bit, which confirms whether an FPGA’s bitstream truly matches the intended gate-level netlist. Another is Ensofic, a silicon attestation platform that combines soft sensors with machine learning to evaluate both the reliability and authenticity of an FPGA, including the ability to spot counterfeit devices. The talk will also cover what it takes to turn research prototypes into practical, commercial-grade solutions ready for deployment in high-stakes industries like aerospace, automotive, defense, and energy. Drawing on hands-on experience with deployed commercial solutions, Dr. Graf will outline key lessons learned and show how these projects have inspired unexpected new applications. The result is a clear picture of challenges and how the security of custom computing machines can advance rapidly in the years ahead.
• Trevor E. Carlson, Associate Professor, National University of Singapore
  Side-channel attacks using power- and EM-based methods have long been demonstrated in traditional ASIC systems. But, other physical side-channels have also played a role in reconfigurable hardware systems, including the detection of voltage changes in shared FPGA settings. Prior studies have proposed various malicious circuit designs that exploit combinations of traditional FPGA logic resources, i.e., Look-up Tables (LUTs), carry chains (CARRY), routing resources, and flip-flops (FFs). While bitstream checks have been added to the compiler and synthesis flows to mitigate these issues, there remain a number of additional resources of leakage that are an integral part of the FPGA, such as the DSP blocks used for complex mathematical operations, that, up to now, have not been exploited. In this talk, we will discuss two recent works that explain FPGA components as side channels. In the first work, LeakyDSP, I will discuss the use of DSP blocks to sense fine-grained voltage fluctuations, and in our other recent work, AmpereBleed, I will discuss how widely available sensors in ARM-FPGA SoCs can be used to exploit current-based side-channels. Taken together, this presentation aims to demonstrate that modern FPGA SoCs remain vulnerable to side-channel attacks, and that we need to continue to work to build new protections to prevent these recently discovered attacks.
• Barbora Hrda, TUM
• Zhuoran Liu, Radboud University
• Nicolai Müler, Ruhr University Bochum
• Francesco Regazzoni, USI and University of Amsterdam
• Shreejith Shanker, Trinity College Dublin
• Jo Vliegen, ES&S/COSIC, ESAT, KU Leuven, Diepenbeek, Belgium

For more information about the talks, please visit the workshop website. The complete timetable is also available on the workshop schedule page.

Interest in hardware security and secure computing systems continues to grow. Recent events have raised awareness of security in general-purpose processors. However, addressing security in custom computing machines is also of high importance, given their increasing use in environments where security and privacy are paramount, including defense, medical, transportation, and communication systems. The SCCM workshop allows researchers in this space to present recent work, discuss current security priorities, and collaborate on future research directions.

FIRE-NL: Workshop on FPGA Innovation Research Exchange in the Netherlands

Type: Workshop

Organizers:
Nikolaos Alachiotis, Assistant professor, University of Twente, The Netherlands
Zaid Al-Ars, Associate professor, Delft University of Technology, The Netherlands
Roel Jordans, Assistant Professor, Eindhoven University of Technology, The Netherlands
Mohsen Safari, Advisor, SURF (where it hosts Dutch national supercomputer Snellius), The Netherlands

The workshop at FPL2025 will highlight the growing importance of FPGA technology for high-performance computing and data analytics (HPCDA), emphasizing its superior energy efficiency compared to GPUs and CPUs. Despite these advantages, FPGA adoption remains limited due to complex programming and lack of awareness beyond the FPGA community. Building on the success of the FIRE initiative and the HW Acceleration Network NL, which have fostered a vibrant Dutch FPGA ecosystem, this workshop aims to showcase Dutch research, catalyze international collaboration, and address emerging challenges in adaptive computing platforms that combine FPGAs with CPUs and AI accelerators.

FPGAs in Action: Real-World Neuromorphic Computing Applications

Type: Tutorial

Organizers/speakers:
Chang Gao, Assistant professor, Delft University of Technology, The Netherlands
Antonio Rios-Navarro, Associate Professor, University of Seville, Spain
Qinyu Chen, Assistant professor, Leiden University, The Netherlands
Tobi Delbruck, Professor of Physics and Electrical Engineering, ETH Zurich, Switzerland

This tutorial will provide a comprehensive overview of the practical application and deployment of neuromorphic computing systems using FPGAs. Moving beyond theoretical aspects and simulations, it will focus on real-world case studies, implemented systems, and tangible results, with special emphasis on the intersection of event-driven sensing and robotics. The tutorial will showcase successful applications where FPGAs power neuromorphic solutions in domains such as robotics, autonomous systems, healthcare, and IoT. It will cover neuromorphic sensing and perception for robotics, demonstrating how event-driven computation enables tasks like object recognition, tracking, and robot navigation. Participants will learn about hardware-software co-design challenges and strategies for mapping complex neuromorphic algorithms efficiently to FPGA architectures.

Featured Talks

Designing the Neuromorphic Auditory Sensor (NAS): From Bio-inspiration to FPGA Implementation

Prof. Antonio Ríos Navarro, Department of Computer Architecture and Technology, University of Seville, Spain

Email: arios@us.es

Biography:

Antonio Ríos-Navarro is an Associate Professor in the Department of Computer Architecture and Technology at the University of Seville, Spain, where he is a member of the Robotics and Technology of Computers Lab. His research focuses on AI hardware and neuromorphic computing, with an emphasis on developing real-time, efficient systems on FPGAs and SoCs for applications such as event-based vision and auditory, autonomous robot navigation, and hardware acceleration for deep learning.

Abstract:

In this talk, we will provide a detailed look into the design and implementation of the Neuromorphic Auditory Sensor (NAS). We will explore how this bio-inspired sensor mimics the human cochlea by utilizing a cascading architecture of spiking filters to replicate the function of the basilar membrane. The session will cover the specific challenges and successful strategies for implementing this complex architecture on FPGAs. Furthermore, we will delve into the accompanying software ecosystem developed to configure the NAS and visualize its real-time output, showcasing the complete workflow from hardware design to data analysis. Finally, we will discuss the exciting evolution of the NAS from its FPGA prototype to its more recent integration into a dedicated ASIC, highlighting the path to more power-efficient and scalable solutions.

FPGA neural network event camera denoising and nonlinear robot control

Prof. Tobi Delbruck, Institute of Neuroinformatics, University of Zurich and ETH Zurich

Email: tobi@ini.uzh.ch

Biography:

Tobi Delbruck received the B.Sc. degree in physics from the University of California in 1986 and PhD degree from Caltech in 1993 as the first student with the newly-established CNS program, with main PhD supervisor Carver Mead. He is an ETH Professor of Physics and Electrical Engineering, and has a position with the Institute of Neuroinformatics, University of Zurich and ETH Zurich, where he has been since 1998. The Sensors group that he co-directs together with Prof. Shih-Chii Liu works on a broad range of topics covering device physics to computer vision and control, with a theme of efficient neuromorphic sensory processing and deep neural network theory and hardware accelerators.

Abstract:

This talk will cover applications of low-cost SoC FPGAs to implement small but quick neural networks for event camera denoising and nonlinear robot control. 1) Event cameras are vision sensors that mimic biology's activity-driven digital output. They offer a unique combination of low latency, high dynamic range, and sparse output that makes them suitable candidates for battery-powered embedded vision systems. They have significant amounts of noninformative noise that wastes power to process. I will describe our development of a tiny FPGA neural network that filters out this noise while preserving informative signal events. 2) Nonlinear optimal control conventionally has been solved by expensive model predictive control (MPC). I will discuss our recent developments of small FPGA neural networks on FPGAs that clone the behavior of MPCs. With these networks, we demonstrated ultra-quick nonlinear control of cartpole and F1TENTH race cars.

Neuromorphic AI-Enhanced Eye Tracking System in Extended Reality

Dr. Qinyu Chen, Leiden Institute of Advanced Computer Science (LIACS) at Leiden University

Email: q.chen@liacs.leidenuniv.nl

Biography:

Qinyu Chen is an assistant professor in the Leiden Institute of Advanced Computer Science (LIACS) at Leiden University, The Netherlands. She received her PhD from Nanjing University, China in 2021. She was a visiting PhD student from 2019 to 2020, and a postdoc from 2022 to 2024, at the Institute of Neuroinformatics, University of Zurich and ETH Zurich, Switzerland. Her current research interest includes the seamless brain-inspired AI system at the edge, and its application in healthcare, generative AI, AR/VR with a focus on event-based processing. She received the 2022 BRIDGE Fellowship from the Swiss National Science Foundation (SNSF) and 2024 Veni Talent Program from Dutch Research Council (NWO).

Abstract:

Eye tracking is a key enabling technology in emerging applications such as extended reality (XR), where energy-efficient, low-latency, high-precision gaze estimation is essential for immersive and intuitive user experiences. However, conventional frame-based eye tracking systems are often constrained by high latency, power consumption, and limited robustness in dynamic environments. This talk presents a new generation of neuromorphic, event-based eye tracking systems inspired by the human retina. A complete pipeline will be introduced, from design considerations, dataset creation, algorithm development to system-level hardware integration using FPGA and ASIC. These solutions achieve state-of-the-art performance in accuracy, energy efficiency, and responsiveness, paving the way for practical deployment in extended reality (XR) headsets.

Energy-Efficient Recurrent Neural Network FPGA Accelerators for Real-Time Inference

Dr. Chang Gao, Department of Microelectronics, Delft University of Technology

Email: chang.gao@tudelft.nl

Biography:

Chang Gao received his Ph.D. degree with Distinction in Neuroscience from the Institute of Neuroinformatics, University of Zurich and ETH Zurich, in 2022 and his master degree from Imperial College London in 2016 and his bachelor degree from University of Liverpool and Xi'an Jiaotong-Liverpool University in July 2015. In August 2022, he joined the Delft University of Technology, The Netherlands, as an Assistant Professor in the Department of Microelectronics. He is leading the Lab of Efficient Machine Intelligence (EMI), working on research in neuromorphic algorithm-hardware co-design for real-time edge AI and its applications in audio processing, computer vision and wireless communication.

Abstract:

Recurrent neural networks (RNNs) are powerful for processing sequential data but are computationally demanding, making CPUs and GPUs inefficient for real-time and edge applications. This talk presents customized hardware accelerators that exploit temporal and spatio-temporal sparsity in GRU- and LSTM-RNNs to achieve low-latency, energy-efficient inference. We first introduce DeltaRNN, the first accelerator to leverage temporal sparsity in GRU-RNNs, delivering 1.2 TOp/s effective throughput, which is 15x higher than prior work. Building on this, EdgeDRNN reduces off-chip memory traffic, achieving 4x higher energy efficiency than NVIDIA Jetson Nano for edge inference. These accelerators enable real-world applications, including continuous speech recognition with a dynamic auditory sensor, ultra-low-power keyword spotting, and stable robotic prosthesis control with 21 µs latency. Finally, we present Spartus, a novel accelerator for LSTM-RNNs combining delta networks with structured pruning to induce spatio-temporal sparsity. Spartus achieves 9.4 TOp/s effective throughput within a 10 W power budget, supporting million-parameter models with microsecond-level inference.