Exploring the new AMD AUP-ZU3 Academic Platform

Type: Tutorial

Organizers/Speakers: Mario Ruiz, AMD University Program, AMD

This tutorial will introduce the AUP-ZU3, the latest AMD University Program SoC academic platform. This platform is designed to serve education and research, catering for both learners and experienced users. This board can be used in multiple areas, including digital design, computer architecture and embedded systems, among others. The AUP-ZU3 board is powered by a ZU3 AMD Zynq™ Ultrascale+™ MPSoC device and it features a variety of interfaces (I/O) - LEDs, switches, buttons, Pmod™, MIPI, Display Port, etc. - that makes it applicable broadly in academia. It is also supported by the popular open source PYNQ framework. As part of the tutorial, we will cover the Vivado™ design flow and how to target the AUP-ZU3 platform. We will discuss what is new in Vivado and Vitis™ HLS. This will give the audience an idea of the development flow not only for the AUP-ZU3 but also for other adaptive computing devices. Then, we will describe how PYNQ™ - Python productivity for adaptive computing platforms - uses Python and Jupyter™ notebooks to make AMD SoC more accessible. We will demonstrate this with a few examples on the AUP-ZU3 board. We will talk about the latest PYNQ (release 3.1) features and how they help its users be more productive. In the second part, the participants will engage in a hands-on session with the newest AUP-ZU3 board, booting it up and exploring example designs using PYNQ. Advanced users will have the opportunity to design their own overlays and download it onto the board. By participating in this tutorial, attendees will gain valuable practical skills that can be directly applied in educational and research settings.

Workshop on Security for Custom Computing Machines (SCCM)

Type: Workshop

Organizers:
Mirjana Stojilović, Scientist, EPFL, Switzerland
Jeff Goeders, Associate Professor, Brigham Young University, United States

Featured Speakers:

• Durga Lakshmi-Ramachandran, Innovation Director, Keysight Device Security Solutions
  This talk will focus on Known Key Analysis in PQC, with a focus on Dilithium signing schemes. It will explore techniques used to recover cryptographic keys and discuss the broader implications for building secure, future-proof cryptographic architectures.
• Guy Gogniat, Professor, Université Bretagne Sud
  In this talk we will discuss some contributions to the security of processor-based systems in the context of embedded devices. We will discuss a solution to ensure constant-time computation and how the cache architecture can be extended to ensure constant-time properties. This approach exploits the software-hardware interface by extending ISA RISC-V to lock and unlock some sensitive data in the cache.
• Jonathan Graf, CEO, Graf Research
  How our bitstream assurance work is opening up new areas of application in automotive, defense, avionics, information assurance, etc. I have some real-world examples of the creative ways our contributions are being implemented by our end users to solve security problems in configurable computing that go beyond even our initial vision for them.
• Trevor E. Carlson, Associate Professor, National University of Singapore
  Understanding and Exploiting FPGA SoC Components to Compromise System Secrets

Interest in hardware security and secure computing systems continues to grow. Recent events have raised awareness of security in general-purpose processors. However, addressing security in custom computing machines is also of high importance, given their increasing use in environments where security and privacy are paramount, including defense, medical, transportation, and communication systems. The SCCM workshop allows researchers in this space to present recent work, discuss current security priorities, and collaborate on future research directions.

FIRE-NL: Workshop on FPGA Innovation Research Exchange in the Netherlands

Type: Workshop

Organizers:
Nikolaos Alachiotis, Assistant professor, University of Twente, The Netherlands
Zaid Al-Ars, Associate professor, Delft University of Technology, The Netherlands
Roel Jordans, Assistant Professor, Eindhoven University of Technology, The Netherlands
Mohsen Safari, Advisor, SURF (where it hosts Dutch national supercomputer Snellius), The Netherlands

The workshop at FPL2025 will highlight the growing importance of FPGA technology for high-performance computing and data analytics (HPCDA), emphasizing its superior energy efficiency compared to GPUs and CPUs. Despite these advantages, FPGA adoption remains limited due to complex programming and lack of awareness beyond the FPGA community. Building on the success of the FIRE initiative and the HW Acceleration Network NL, which have fostered a vibrant Dutch FPGA ecosystem, this workshop aims to showcase Dutch research, catalyze international collaboration, and address emerging challenges in adaptive computing platforms that combine FPGAs with CPUs and AI accelerators.

FPGAs in Action: Real-World Neuromorphic Computing Applications

Type: Tutorial

Organizers/speakers:
Chang Gao, Assistant professor, Delft University of Technology, The Netherlands
Antonio Rios-Navarro, Associate Professor, University of Seville, Spain
Qinyu Chen, Assistant professor, Leiden University, The Netherlands
Tobi Delbruck, Professor of Physics and Electrical Engineering, ETH Zurich, Switzerland

This tutorial will provide a comprehensive overview of the practical application and deployment of neuromorphic computing systems using FPGAs. Moving beyond theoretical aspects and simulations, it will focus on real-world case studies, implemented systems, and tangible results, with special emphasis on the intersection of event-driven sensing and robotics. The tutorial will showcase successful applications where FPGAs power neuromorphic solutions in domains such as robotics, autonomous systems, healthcare, and IoT. It will cover neuromorphic sensing and perception for robotics, demonstrating how event-driven computation enables tasks like object recognition, tracking, and robot navigation. Participants will learn about hardware-software co-design challenges and strategies for mapping complex neuromorphic algorithms efficiently to FPGA architectures.